1. Field of the Invention
The present invention relates generally to integrated circuit packaging, and in particular to a structure and method for minimizing the lead length between a passive electronic device and an integrated circuit.
2. Description of Related Art
Semiconductor devices having high and dense lead counts and operating at high speeds require very short leads to ensure noiseless signal propagation. Noise can be introduced onto a lead by other nearby signal leads. Additionally, passive devices or components, such as resistors, capacitors, inductors and filters, add to the length of signal leads within an assembly. As used herein, the term "semiconductor device" or "device" refers to an integrated circuit chip or die containing circuitry. The "carrier" refers to the substrate material upon which the device is attached and contains internal circuitry that is used to interface the device with other electronic components. The "semiconductor device assembly" or "assembly" refers to the semiconductor device plus associated carrier containing the device. The "passive" refers to resistors, inductors, filters, capacitors and any combination attached to the carrier and/or device as a component of the assembly. A "board" is a structure that is used to hold a plurality of carriers.
The lead length effect is highly affected by the capacitor type passive component. It is highly desirable to locate the capacitors as close to the semiconductor device as possible. It is a common practice to mount capacitors external to the semiconductor device. In some carriers, the capacitors may be mounted on the same plane as the device but off to one side or another. Another carrier structure might attach the capacitor within a socket or cavity on the carrier. In either case, the capacitor is "remotely" located away from the semiconductor device. As the distance from the capacitor to the semiconductor device increases, the capacitor's efficiency and effectiveness are adversely affected. Problems that can occur include stray inductances, ground plane bounce, and voltage surges.
Attempts in the prior art to reduce lead lengths has not resolved these problems. For example, U.S. Pat. No. 5,210,683 discloses an assembly for mounting a capacitor, external to a semiconductor device, within a well or cavity that is formed in the assembly in close proximity to the device such that it is located within the assembly and thereby somewhat reducing the lead or via length. However, the major problem of connectivity to the device, without electrical noise still exists with this structure.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a structure and method for minimizing the lead length between a passive electronic component, a carrier or board, and an electronic device.
It is another object of the present invention to provide a structure and method to minimize the distance between a passive electronic device and a semiconductor device.
A further object of the invention is to provide a method and structure to minimize the length of signal leads within a semiconductor device assembly.
It is yet another object of the present invention to provide a method and structure to minimize the ability of electrical noise to be induced onto nearby signal leads.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.